Client: Our client a leading MultinationalSemiconductor PowerCompany requiresSenior Analog Mixed Signal Design Engineerfor position based in Catania, Italy.
Role: The Team is expanding its focus inPower Solutions, across a broad range of IC engineering profiles and levels of experience, including Analog Designer, Digital Designer, Mixed-Signal Designer, Verification Engineer, Silicon Evaluation Engineer and Layout Designer.
The candidate will be involved in the following developments, from definition to production:
LDO, BUCK, BOOST, BUCK-BOOST, CHARGE-PUMP, SIMO (Single-Input / Multiple Outputs)IBB (Inverted BUCK-BOOST), ICP (Inverted CHARGE-PUMP), Negative LDOPower Sequencer, Oscillators, PLL, Bandgap, References, ADC, DAC, I/O, SPI, I2C, SPMI, OTP, MTP, RAM, ROM, DFTResponsibilities: Mixed-Signal Verification IP DevelopmentImprove AMS Verification Team Flows & MethodologiesBridge AMS / DMS Verification and Bench Evaluation environmentsPower Management IC DevelopmentIntegrate IPs, improve Integration Flows & MethodologiesExecute on PMIC pre-silicon AMS verification and support PMIC post-silicon bench evaluationExecute for 100% PMIC verification coverage, combining DMS and AMS, Top-Level and IP-LevelTechnical Customer Interface EngagementParticipate in customer engagements, in support of technical feasibility and proposalsIC Milestone WorkshopsHuman Resources ManagementProvide Mentorship and technical leadership, setting up framework and structure for efficient development flowsEnable a culture of continuous learning and improvementSupport project management and task planning Qualifications; Degree in Electrical Engineering, Computer Science, or Computer EngineeringExperienceYou will have 5+ years of experienceIC AMS Verification Leading experience with multiple products introduced into the marketMixed-Signal Verification methodology and tools (AMS / APS / Flex)Good understanding of Mixed-Signal Design Flow and Top-Down development methodologyGreat technical and analytical background with good problem-solving skillsGreat team worker with multi-discipline, multi-cultural and multi-site environmentsAnalog Functional and Parametric VerificationProcess - Voltage - Temperature (PVT) Corners, Layout Parameter Extraction (LPE) SimulationsAnalog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)Good written and verbal communicationPreferred Qualifications & Experience: Proficient with Cadence Suite (Virtuoso ADE Spectre)Scripting languages (Shell, TCL, PERL, Python)HDL programming languages (Verilog / SystemVerilog)Good understanding of Power IP TopologiesExperience with Multiple Power and Clock domainsIC Top-Level Digital UVM Environment Setup & Verification (Universal Verification Methodology)Verification Planning tools (ePlanner, vManager)Functional Oriented and Randomized Verification, Gate Level Simulation (GLS)Property Specification Language (PSL), SystemVerilog Assertions (SVA)Regressions and CoverageLab silicon bring-up evaluation and Production Test support experiencesContact: For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email ******
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